Mismatch independent DNL pipelined analog to digital converter

John Wu, Bosco Leung, Sehat Sutarja

研究成果: 雜誌貢獻Conference article同行評審

6 引文 斯高帕斯(Scopus)

摘要

A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.
原文英語
頁(從 - 到)461-464
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
5
出版狀態已發佈 - 十二月 1 1994
對外發佈
事件Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
持續時間: 五月 30 1994六月 2 1994

ASJC Scopus subject areas

  • 電氣與電子工程
  • 電子、光磁材料

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