摘要
This paper describes the advantages of integrating a common Power Clamp with the ability to withstand voltage and save on wafer area. The system chip does not require a power clamp for each input source. It is as long as the system core circuit by electrostatic protection. It can reach normal operation and save as much chip area as possible. The structure of this paper has three main features: (1) electrostatic protection (ESD) circuit common Power Clamp combination (2) T025 process high and low voltage ESD (3) The experiment and results within ESD system. The results of ESD sensitivity passed is-6250V~+6200V for type HBM mode. It is-375V~+375V for type MM mode.
原文 | 英語 |
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主出版物標題 | Proceedings - 3rd International Conference on Green Technology and Sustainable Development, GTSD 2016 |
發行者 | Institute of Electrical and Electronics Engineers Inc. |
頁面 | 78-81 |
頁數 | 4 |
ISBN(電子) | 9781509036387 |
DOIs | |
出版狀態 | 已發佈 - 十二月 22 2016 |
對外發佈 | Yes |
事件 | 3rd International Conference on Green Technology and Sustainable Development, GTSD 2016 - Kaohsiung, 臺灣 持續時間: 十一月 24 2016 → 十一月 25 2016 |
會議
會議 | 3rd International Conference on Green Technology and Sustainable Development, GTSD 2016 |
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國家 | 臺灣 |
城市 | Kaohsiung |
期間 | 11/24/16 → 11/25/16 |
ASJC Scopus subject areas
- Environmental Science (miscellaneous)
- Environmental Engineering