An algorithm for generating boolean expressions in VHDL based on ladder diagrams

Hongxia Xie, Zheng Yun Zhuang

研究成果: 雜誌貢獻文章同行評審

2 引文 斯高帕斯(Scopus)

摘要

This study proposes an algorithm for generating the associated Boolean expression in VHDL, given a ladder diagram (LD) as the input. The purpose of the algorithm is to implement of field-programmable gate array-(FPGA-) based programmable logic controllers (PLCs), where an effective conversion from an LD to its associated Boolean expressions seems rarely mentioned. Based on this core thought, the conversion process of the algorithm first involves abstracting and expressing the encountered LD as an activity-on-vertex (AOV) graph. Next, an AND-OR tree in which AND-nodes and OR-nodes connote the series and the parallel relationships between the vertices of the AOV graph is constructed based on the AOV graph. Therefore, by a traversal to the AND-OR tree, the associated Boolean expression, as the output of the algorithm, can be easily obtained in VHDL. The proposed algorithm is then verified with an illustrative example, wherein a complicated LD is given as the input.
原文英語
文章編號530586
期刊Mathematical Problems in Engineering
2015
DOIs
出版狀態已發佈 - 2015
對外發佈

ASJC Scopus subject areas

  • 數學(全部)
  • 工程 (全部)

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