Three-dimensional architecture of multiplexing data registration integrated circuit for large-array ink jet printhead

Jian Chiun Liou, Fan Gang Tseng

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This article proposes a novel architecture of high selection speed three-dimensional data registration circuit for ink jet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array ink jet printheads with nozzles numbering more than 1000. This integrated circuit architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection, address, and power supply, will be employed together to activate a nozzle for droplet ejection. The total number of data accessing points of the three-dimensional configuration will be the cubic root of the nozzle number with each jet controlled by five input lines, including multiplexing data latches and shift registers. The simulation and experiment results demonstrated a reduction of scanning time by up to 67% thanks to the reduction of lines for scanning when compared to a two-dimensional configuration. The total circuit area, 2500×2500 μm2, will be 80% of the circuit area by three-dimensional configuration for 1000 nozzles. This device has been designed, fabricated by CMOS 0.35 μm process, and characterized.

Original languageEnglish
Pages (from-to)10508-105087
Number of pages94580
JournalJournal of Imaging Science and Technology
Volume52
Issue number1
DOIs
Publication statusPublished - Jan 2008
Externally publishedYes

Fingerprint

inks
multiplexing
Multiplexing
Ink
nozzles
integrated circuits
Integrated circuits
Nozzles
configurations
Scanning
resistors
Resistors
scanning
Networks (circuits)
Transistors
transistors
latches
shift registers
Shift registers
registers

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Chemistry(all)
  • Atomic and Molecular Physics, and Optics
  • Computer Science Applications

Cite this

Three-dimensional architecture of multiplexing data registration integrated circuit for large-array ink jet printhead. / Liou, Jian Chiun; Tseng, Fan Gang.

In: Journal of Imaging Science and Technology, Vol. 52, No. 1, 01.2008, p. 10508-105087.

Research output: Contribution to journalArticle

@article{4af4702a4db94e6691ed9a0a99f03561,
title = "Three-dimensional architecture of multiplexing data registration integrated circuit for large-array ink jet printhead",
abstract = "This article proposes a novel architecture of high selection speed three-dimensional data registration circuit for ink jet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array ink jet printheads with nozzles numbering more than 1000. This integrated circuit architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection, address, and power supply, will be employed together to activate a nozzle for droplet ejection. The total number of data accessing points of the three-dimensional configuration will be the cubic root of the nozzle number with each jet controlled by five input lines, including multiplexing data latches and shift registers. The simulation and experiment results demonstrated a reduction of scanning time by up to 67{\%} thanks to the reduction of lines for scanning when compared to a two-dimensional configuration. The total circuit area, 2500×2500 μm2, will be 80{\%} of the circuit area by three-dimensional configuration for 1000 nozzles. This device has been designed, fabricated by CMOS 0.35 μm process, and characterized.",
author = "Liou, {Jian Chiun} and Tseng, {Fan Gang}",
year = "2008",
month = "1",
doi = "10.2352/J.ImagingSci.Technol.(2008)52:1(010508)",
language = "English",
volume = "52",
pages = "10508--105087",
journal = "Journal of Imaging Science and Technology",
issn = "1062-3701",
publisher = "Society for Imaging Science and Technology",
number = "1",

}

TY - JOUR

T1 - Three-dimensional architecture of multiplexing data registration integrated circuit for large-array ink jet printhead

AU - Liou, Jian Chiun

AU - Tseng, Fan Gang

PY - 2008/1

Y1 - 2008/1

N2 - This article proposes a novel architecture of high selection speed three-dimensional data registration circuit for ink jet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array ink jet printheads with nozzles numbering more than 1000. This integrated circuit architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection, address, and power supply, will be employed together to activate a nozzle for droplet ejection. The total number of data accessing points of the three-dimensional configuration will be the cubic root of the nozzle number with each jet controlled by five input lines, including multiplexing data latches and shift registers. The simulation and experiment results demonstrated a reduction of scanning time by up to 67% thanks to the reduction of lines for scanning when compared to a two-dimensional configuration. The total circuit area, 2500×2500 μm2, will be 80% of the circuit area by three-dimensional configuration for 1000 nozzles. This device has been designed, fabricated by CMOS 0.35 μm process, and characterized.

AB - This article proposes a novel architecture of high selection speed three-dimensional data registration circuit for ink jet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array ink jet printheads with nozzles numbering more than 1000. This integrated circuit architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection, address, and power supply, will be employed together to activate a nozzle for droplet ejection. The total number of data accessing points of the three-dimensional configuration will be the cubic root of the nozzle number with each jet controlled by five input lines, including multiplexing data latches and shift registers. The simulation and experiment results demonstrated a reduction of scanning time by up to 67% thanks to the reduction of lines for scanning when compared to a two-dimensional configuration. The total circuit area, 2500×2500 μm2, will be 80% of the circuit area by three-dimensional configuration for 1000 nozzles. This device has been designed, fabricated by CMOS 0.35 μm process, and characterized.

UR - http://www.scopus.com/inward/record.url?scp=41649084572&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=41649084572&partnerID=8YFLogxK

U2 - 10.2352/J.ImagingSci.Technol.(2008)52:1(010508)

DO - 10.2352/J.ImagingSci.Technol.(2008)52:1(010508)

M3 - Article

AN - SCOPUS:41649084572

VL - 52

SP - 10508

EP - 105087

JO - Journal of Imaging Science and Technology

JF - Journal of Imaging Science and Technology

SN - 1062-3701

IS - 1

ER -