Mismatch independent DNL pipelined analog to digital converter

John Wu, Bosco Leung, Sehat Sutarja

Research output: Contribution to journalConference article

6 Citations (Scopus)

Abstract

A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.

Original languageEnglish
Pages (from-to)461-464
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
Publication statusPublished - Dec 1 1994
Externally publishedYes
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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