An algorithm for generating boolean expressions in VHDL based on ladder diagrams

Hongxia Xie, Zheng Yun Zhuang

Research output: Contribution to journalArticle

Abstract

This study proposes an algorithm for generating the associated Boolean expression in VHDL, given a ladder diagram (LD) as the input. The purpose of the algorithm is to implement of field-programmable gate array-(FPGA-) based programmable logic controllers (PLCs), where an effective conversion from an LD to its associated Boolean expressions seems rarely mentioned. Based on this core thought, the conversion process of the algorithm first involves abstracting and expressing the encountered LD as an activity-on-vertex (AOV) graph. Next, an AND-OR tree in which AND-nodes and OR-nodes connote the series and the parallel relationships between the vertices of the AOV graph is constructed based on the AOV graph. Therefore, by a traversal to the AND-OR tree, the associated Boolean expression, as the output of the algorithm, can be easily obtained in VHDL. The proposed algorithm is then verified with an illustrative example, wherein a complicated LD is given as the input.

Original languageEnglish
Article number530586
JournalMathematical Problems in Engineering
Volume2015
DOIs
Publication statusPublished - 2015
Externally publishedYes

Fingerprint

Computer hardware description languages
Ladders
Diagram
Vertex of a graph
Field programmable gate arrays (FPGA)
Graph in graph theory
Programmable Logic Controller
Programmable logic controllers
Field Programmable Gate Array
Series
Output

ASJC Scopus subject areas

  • Mathematics(all)
  • Engineering(all)

Cite this

An algorithm for generating boolean expressions in VHDL based on ladder diagrams. / Xie, Hongxia; Zhuang, Zheng Yun.

In: Mathematical Problems in Engineering, Vol. 2015, 530586, 2015.

Research output: Contribution to journalArticle

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